Graphic processor and graphic processing system

ABSTRACT

The rendering performance of a graphic processor is improved by effectively using a data bus. An externally-input graphics command is stored in a work memory via the data bus. A display data generation section receives a graphics command stored in the work memory via the data bus, decodes the received graphics command, and outputs the display data to the data bus. An image display section receives display data stored in the work memory via the data bus, and displays an image on a display device. A bus control section monitors the status of use of the data bus, and controls the right to use the data bus according to the priority of each data transfer operation.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a graphic processor forrendering computer graphics elements.

[0002] In recent years, the computer graphics (CG) technology has seen aremarkable progress. Typical applications of computer graphics includeCAD, CAE, video games, etc. Recently, computer graphics has also beenused for displaying map information such as in car navigation systems.

[0003] Computer graphics requires a graphics command for performing agraphic operation and coordinate data of an element to be rendered. Atexture mapping technique of applying a texture on an element requirestexture data representing the texture to be applied on the object. Inrecent years, along with the increase in the amount of data which can beprocessed, there is a demand for a finer graphic operation, whereby theamount of rendering data required has been ever increasing. Whilecomputer graphics also requires a frame buffer for storing image data ofa display screen, the size of the display screen has also beenincreasing. As a result, a contemporary graphic processor requires awork memory with a huge storage capacity.

[0004] Conventionally, a data memory to be the work area for processingthe rendering data and a frame memory to be the rendering area forstoring display data are configured separately. Recently, a unifiedmemory architecture (UMA) has been proposed in the art, where the workarea and the rendering area are configured in a single memory. In theunified memory architecture, the relationship between the graphicprocessor and the memory is uniquely determined, thereby simplifying thesystem configuration and significantly reducing the cost.

[0005]FIG. 10 is a block diagram illustrating a configuration of aconventional graphic processor. Referring to FIG. 10, a graphicprocessor 200 receives, via an external bus 201, a graphics commandwhich is generated between a CPU 202 and a memory 203. The receivedgraphics command is supplied from a CPU interface 211 to a FIFO memory215 via a first data bus 213. The graphics command received by the FIFOmemory 215 is decoded by graphics command decoding means 216, andrendering means 218 performs the graphic operation according to thedecoding result. Display data obtained by the graphic operation issupplied from a memory interface 212 to a work memory 204 via a seconddata bus 214. The display data stored in the work memory 204 is suppliedto display means 219 via the second data bus 214 and displayed on adisplay device 205.

[0006] Thus, while an externally-input graphics command is supplied tothe FIFO memory 215 via the first data bus 213, the other data istransferred between the CPU interface 211 and the memory interface 212via the second data bus 214.

[0007] Problems to be Solved

[0008] Possible approaches to increase the data transfer rate for thepurpose of improving the rendering performance include, for example, toimprove the operating speed (clock rate) or to increase the bus width ofa data bus. However, an increase in the operating speed creates otherproblems such as an increase in the power consumption. Therefore, inmany cases, the data bus width is increased. However, since theconventional graphic processor as described above requires at least twodata buses, the increase in the bus width may lead to a significantincrease in cost in a case where the graphic processor is implemented inan LSI.

[0009] Another possible approach is to share a data bus. In such a case,however, a plurality of types of data flow along the single data bus,whereby data transfer operations may contend with one another, leadingto other problems, e.g., it may be difficult to ensure a desirablegraphics command supply rate, or the displayed image may be intermitted.A possible solution to such problems is, for example, to substantiallyincrease the storage capacity of an internal memory. However, such asolution also leads to a significant increase in cost.

[0010] A graphics command is typically variable-length data, notfixed-length data. This is because coastlines, residential blocks, etc.,used in map rendering as in car navigation systems, for example, requireelement data consisting of a series of many coordinate points whichcannot be represented by simple triangles and/or rectangles.

[0011] For example, a road, or the like, is represented by a series ofstraight lines as illustrated in FIG. 11A, and a graphics command forrendering such a series of straight lines contains a plurality ofcoordinate points constituting the series of straight lines asillustrated in FIG. 11B. A residential block, or the like, isrepresented by a polygon as illustrated in FIG. 12A, and a graphicscommand for rendering such a polygon contains a plurality of coordinatepoints constituting the boundary line thereof as illustrated in FIG.12B.

[0012] Where the inside of the element as illustrated in FIG. 12A isfilled, in order to quickly complete a graphic operation, the fillingoperation cannot be performed until the boundary line has been drawn.Accordingly, it is indispensable to quickly complete drawing theboundary line. Therefore, for animation display with scrolling at a timeinterval of, for example, {fraction (1/30)} sec or {fraction (1/60)}sec, it is necessary to supply sufficient coordinate data required forthe graphic operation. The operation of filling the inside of an elementcan be performed according to, for example, the algorism disclosed in“Jissen Computer Graphics”, Nikkan Kogyo, pp. 100-102.

[0013] In order to reliably supply a graphics command containing suchvariable-length data with the above-described conventional example, itis necessary for the CPU to control the FIFO memory storing the graphicscommand of the graphic processor at a predetermined time interval. Insuch a case, however, a substantial load is imposed on the CPU, and theload is particularly significant when processing a graphics command witha great data length. However, since the CPU performs OS operations forthe graphic processing system as a whole, such a load on the CPU maydeteriorate the overall performance or response speed of the system.While improving the performance of the CPU is of course a possiblesolution, it will increase the system cost. A possible approach toreduce the load on the CPU is to increase the storage capacity of theFIFO, but this also lead to an increase in cost.

SUMMARY OF THE INVENTION

[0014] An object of the present invention is to improve the renderingperformance of a graphic processor by effectively using a data bus.

[0015] Specifically, the present invention provides a graphic processor,including: a first interface for receiving an externally-input graphicscommand; a second interface for performing a data transfer operationbetween the graphic processor and a work memory; a data bus fortransferring data between the first interface and the second interface;a display data generation section for receiving a graphics command fromthe data bus, generating display data by decoding the graphics command,and outputting the generated display data to the data bus; an imagedisplay section for receiving the display data from the data bus anddisplaying an image on a display device; and a bus control section formonitoring a status of use of the data bus and controlling a right touse the data bus, wherein the bus control section sets a priority foreach data transfer operation along the data bus and controls the rightto use the data bus according to the set priorities.

[0016] According to the present invention, the right to use the data busis controlled by the bus control section according to the priorities ofdata transfer operations. Therefore, even in a case of a data bus whichis connected to a system such as a unified memory and handles aplurality of types of data in a unified manner, it is possible toeffectively use the data bus without wasting a vacant status thereof.Thus, it is possible to efficiently supply graphics commands, therebyimproving the overall efficiency of the graphic processing system.

[0017] It is preferred that the bus control section in the graphicprocessor of the present invention sets a priority for each of at leastthe following data transfer operations: a data transfer operation oftransferring an externally-input graphics command to the work memory; adata transfer operation of supplying a graphics command from the workmemory to the display data generation section; and a data transferoperation of supplying display data from the work memory to the imagedisplay section.

[0018] It is preferred that the bus control section in the graphicprocessor of the present invention is configured so that a setting ofthe priorities of data transfer operations can be changed dynamically.

[0019] It is preferred that the graphic processor further includes: apre-decoding section for pre-decoding a graphics command transferredduring a data transfer operation of transferring an externally-inputgraphics command to the work memory; and a processing amount estimatingsection for estimating a data processing amount at the display datageneration section based on a result of the pre-decoding by thepre-decoding section, wherein the bus control section changes thepriorities of the data transfer operations according to the dataprocessing amount estimated by the processing amount estimating section.Moreover, it is preferred that when the estimated data processing amountper a predetermined period of time exceeds a predetermined amount, thebus control section sets the priority of a data transfer operation ofsupplying a graphics command from the work memory to the display datageneration section to be higher than the priority of a data transferoperation of transferring an externally-input graphics command to thework memory.

[0020] Alternatively, it is preferred that the graphic processor furtherincludes a memory monitor for monitoring an amount of data of graphicscommands stored in the work memory, wherein the bus control sectionchanges the priorities of the data transfer operations according to thedata amount monitored by the memory monitor. Moreover, it is preferredthat when the monitored data amount is smaller than a predeterminedamount, the bus control section sets the priority of a data transferoperation of transferring an externally-input graphics command to thework memory to be higher than the priority of a data transfer operationof supplying a graphics command from the work memory to the display datageneration section.

[0021] Alternatively, it is preferred that: the first interface isconnected to an external bus which is provided external to the graphicprocessor; an external bus monitor for monitoring an amount of databeing transferred along the external bus is connected to the externalbus; and the bus control section changes the priorities of the datatransfer operations along the data bus according to the amount of databeing transferred which is monitored by the external bus monitor.

[0022] Moreover, it is preferred that: the display data generationsection in the graphic processor of the present invention includes agraphics command storing section for temporarily storing a graphicscommand which is input through the data bus, and a decoding section fordecoding a graphics command which is output from the graphics commandstoring section; the graphics command storing section includes firstdata storing means and second data storing means, writes graphicscommands into selected one of the first and second data storing means ina predetermined address order, and reads out graphics commands fromselected one of the first and second data storing means in apredetermined address order; and when a reading address in one of thefirst and second data storing means from which graphics commands arebeing read out matches a predetermined check address, the graphicscommand storing section starts writing new graphics commands into theone of the first and second data storing means.

[0023] The present invention also provides a graphic processing system,including: the graphic processor according to the present invention; anexternal bus connected to the first interface of the graphic processor;a CPU and a memory which are connected to the external bus; a workmemory connected to the second interface of the graphic processor; and adisplay device connected to the image display section of the graphicprocessor.

[0024] The present invention also provides a graphic processor,including: a first interface for receiving an externally-input graphicscommand; a second interface for performing a data transfer operationbetween the graphic processor and a work memory; a data bus forconnecting the first interface with the second interface; a display datageneration section for receiving a graphics command from the data bus,generating display data by decoding the graphics command, and outputtingthe generated display data to the data bus; and an image display sectionfor receiving the display data from the data bus and displaying an imageon a display device, wherein: the display data generation sectionincludes a graphics command storing section for temporarily storing agraphics command which is input through the data bus, and a decodingsection for decoding a graphics command which is output from thegraphics command storing section; the graphics command storing sectionincludes first data storing means and second data storing means, writesgraphics commands into selected one of the first and second data storingmeans in a predetermined address order, and reads out graphics commandsfrom selected one of the first and second data storing means in apredetermined address order; and when a reading address in one of thefirst and second data storing means from which graphics commands arebeing read out matches a predetermined check address, the graphicscommand storing section starts writing new graphics commands into theone of the first and second data storing means.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]FIG. 1 is a block diagram illustrating a configuration of agraphic processor according to the first embodiment of the presentinvention.

[0026]FIG. 2 is a diagram illustrating an operation of the graphicprocessor of FIG. 1.

[0027]FIG. 3 is a diagram illustrating an internal configuration ofgraphics priority determination means in the configuration of FIG. 1.

[0028]FIG. 4 is an exemplary setting of priorities of data transferoperations.

[0029]FIG. 5 is a diagram illustrating a configuration for addressmanagement of data storing means in the configuration of FIG. 1.

[0030]FIG. 6 is a diagram illustrating the address management of thedata storing means in the configuration of FIG. 1.

[0031]FIG. 7 is a diagram illustrating the address management of thedata storing means in the configuration of FIG. 1.

[0032]FIG. 8 is a block diagram illustrating a configuration of agraphic processor according to the second embodiment of the presentinvention.

[0033]FIG. 9 is a block diagram illustrating a configuration of agraphic processor according to the third embodiment of the presentinvention.

[0034]FIG. 10 is a block diagram illustrating a configuration of aconventional graphic processor.

[0035]FIG. 11A is an exemplary rendering of a series of straight lines.

[0036]FIG. 11B is an exemplary graphics command for a series of straightlines.

[0037]FIG. 12A is an exemplary rendering of an arbitrary-vertex polygon.

[0038]FIG. 12B is an exemplary graphics command for a polygon.

DETAILED DESCRIPTION OF THE INVENTION

[0039] Embodiments of the present invention will now be described withreference to the accompanying drawings.

[0040] FIRST EMBODIMENT

[0041]FIG. 1 is a block diagram illustrating a configuration of agraphic processor according to the first embodiment of the presentinvention. Referring to FIG. 1, a graphic processor 100 includes: a CPUinterface 11 as a first interface for performing an interface controlwith a CPU 102 and receiving a graphics command from the CPU 102; amemory interface 12 as a second interface for performing an interfacecontrol with a work memory 104; a data bus 13 for transferring databetween the CPU interface 11 and the memory interface 12; bus monitoringand controlling means 41 for monitoring the status of a data transferoperation along the data bus 13; graphics priority determination means42 for managing the priorities of data transfer operations along thedata bus 13; a graphics command storing section 22 for temporarilystoring a graphics command; rendering data transfer means 21 forcontrolling the transfer of data from the data bus 13 to the graphicscommand storing section 22; address management means 27 for managing theaddresses of the graphics command storing section 22; graphics commanddecoding means 25 for decoding graphics commands stored in the graphicscommand storing section 22; rendering control means 28 for controlling agraphic operation according to an output from the graphics commanddecoding means 25; rendering means 26 for processing the rendering datareceived via the graphics command decoding means 25 according to therendering control means 28; and an image display section 30 forconverting the rendered data into data to be displayed as an image andcontrolling the display.

[0042] A display data generation section 20 includes the rendering datatransfer means 21, the graphics command storing section 22, the graphicscommand decoding means 25, the rendering means 26, the addressmanagement means 27 and the rendering control means 28. The display datageneration section 20 receives a graphics command from the data bus 13,generates display data by decoding the received graphics command, andoutputs the generated display data to the data bus 13. A bus controlsection 40 includes the bus monitoring and controlling means 41 and thegraphics priority determination means 42. The bus control section 40monitors the status of use of the data bus 13 and controls the right touse the data bus 13.

[0043] The graphics command storing section 22 includes first datastoring means 22 a and second data storing means 22 b. A control line 50is used to control a data transfer operation along the data bus 13, etc.

[0044] The CPU 102 for supplying graphics commands to the graphicprocessor 100, a memory 103 used by the CPU 102 for arithmetic andcontrol operations, an external bus 101 used by the CPU 102 and thememory 103, a display device 105 for displaying image display data whichis output from the graphic processor 100, and the work memory 104, areprovided in addition to the graphic processor 100, together forming agraphic processing system. The work memory 104 is used as a work areafor graphic operations and as a rendering area for storing display data,and has the so-called unified memory architecture (UMA).

[0045]FIG. 2 is a diagram illustrating an operation of the graphicprocessor 100 of FIG. 1. Referring to FIG. 2, first, rendering data({circle over (1)}) recorded on a recording medium 106 such as a DVD, aCD, or the like, is transferred to the memory 103 via the external bus101 ({circle over (2)}). The CPU 102 creates a graphics commandexecutable by the graphic processor 100 from the rendering data storedin the memory 103. The created graphics command is transferred to thework memory 104 via the CPU interface 11, the data bus 13 and the memoryinterface 12 ({circle over (4)}). In this case, the graphics command maybe transferred by the CPU 102, or may be transferred in such a mannerthat there is no direct intervention of the CPU 102, e.g., a DMAtransfer operation.

[0046] Upon recognizing via the rendering control means 28 that thegraphics command has been stored in the work memory 104 ({circle over(5)}), the display data generation section 20 starts a series of graphicoperations. Specifically, the rendering data transfer means 21 transfersa graphics command from the work memory 104 to the graphics commandstoring section 22 ({circle over (6)}). Then, the graphics commandstored in the graphics command storing section 22 is decoded by thegraphics command decoding means 25, and the graphic operation isperformed by the rendering means 26 ({circle over (7)}). The data whichhas been processed in the graphic operation by the rendering means 26 istransferred to the work memory 104 as display data ({circle over (8)}).

[0047] The display data stored in the work memory 104 is transferred tothe image display section 30 and displayed on the display device 105 ata time interval of, for example, {fraction (1/30)} sec or {fraction(1/60)} sec ({circle over (9)}). Thereafter, the series of operations isrepeated.

[0048] In the present embodiment, the bus control section 40 sets apriority of each type of data transfer operation along the data bus 13,and controls the right to use the data bus 13 according to the setpriorities. For example, a priority is set for each of a data transferoperation of transferring an externally-input graphics command to thework memory 104 ({circle over (4)}), a data transfer operation ofsupplying a graphics command from the work memory 104 to the displaydata generation section 20 ({circle over (6)}), and a data transferoperation of supplying display data from the work memory 104 to theimage display section 30 ({circle over (9)}).

[0049]FIG. 3 is a diagram illustrating an exemplary internalconfiguration of the graphics priority determination means 42 of FIG. 1.In the example of FIG. 3, the graphics priority determination means 42includes a priority setting register 42 a and priority comparison means42 b. The priority of each type of data transfer operation along databus 13 is set in the priority setting register 42 a. The prioritycomparison means 42 b recognizes via the control line 50 any devicerequesting a data transfer operation after the current data transferoperation, determines the next data transfer operation to be performedby referencing the contents of the priority setting register 42 a, andinstructs the bus monitoring and controlling means 41. The busmonitoring and controlling means 41 grants the right to use the data bus13 to the device for the next data transfer operation to be performed.

[0050]FIG. 4 is a diagram illustrating an exemplary priority setting. Inthe example of FIG. 4, a smaller priority value indicates a higherpriority. In this example, a display data supply operation is given thehighest priority. This is because if the display data is not supplied ata time interval of, for example, {fraction (1/30)} sec or {fraction(1/60)} sec, a normal graphic operation cannot be performed on thedisplay device 105, whereby noise is carried by the displayed element.

[0051] Note that the priority setting register 42 a is configured sothat the setting stored therein can be externally changed via thecontrol line 50. For example, in the example of FIG. 4, while therendering data writein operation, i.e., the operation of writing therendering data generated from the rendering means 26, is given thelowest priority, this setting can be changed from the CPU 102 via theCPU interface 11, for example. In other words, the bus control section40 is configured so that the setting of the priorities of data transferoperations can be changed dynamically.

[0052] Note that where the data transfer priorities are fixed, thegraphics priority determination means 42 may be implemented with hardlogics instead of using registers.

[0053] Moreover, in this example, the graphics priority determinationmeans 42 starts the next data transfer operation after the current datatransfer operation is completed. However, if, during a data transferoperation, a request for another data transfer operation of a higherpriority, such as the display data supply operation, the rendering datawritein operation, occurs, the current data transfer operation may beonce stopped to first perform the later-requested data transferoperation, after which the first data transfer operation can be resumed.

[0054] Note that where another external device is connected to the databus 13, it is preferred to set a priority of a data transfer operationto be requested by the device. Such data transfer operations includetransferring image data taken by a video camera, transferring broadcastdata such as TV broadcast data (streaming (MPEG4)), transferring imagedata which has been generated by another image generation device andtransmitted therefrom, etc.

[0055] In case of input of such an external moving image, it ispreferable to give a higher priority to moving image data than tographics data.

[0056] Further, the priority of the display operations may be determinedaccording to a location relationship in a multi-window display or thesize of an image to be displayed. For example, in the multi-windowdisplay, the priority of display data of an image to be displayedfurther anteriorly is set higher, or the priority of display data oflarger size is set higher. In case of display data of same size, thepriority of the moving image data is set higher than that of thegraphics data.

[0057]FIG. 5 is a diagram illustrating, in greater detail, a part of theconfiguration of the display data generation section 20 of FIG. 1.Referring to FIG. 5, the address management means 27 includes: a firstcheck address storing register 27 a; a second check address storingregister 27 b; an area setting register 27 c for determining which oneof the first and second check address storing registers 27 a and 27 b isto be used; a selector 27 d for selecting the value of one of the firstand second check address storing registers 27 a and 27 b according tothe value of the area setting register 27 c; and comparison means 27 efor comparing the output from the selector 27 d with the address valuewhich is output by the rendering control means 28 for accessing thegraphics command storing section 22.

[0058] The rendering data transfer means 21 includes data transfercontrol means 21 a for controlling data transfer of a graphics command,and data transfer area setting means 21 b for storing parameters whichare necessary for the control by the data transfer control means 21 a.

[0059] The rendering control means 28 outputs an address to the graphicscommand storing section 22 and reads out a graphics command from one ofthe first and second check address storing registers 27 a and 27 b for agraphic operation. The comparison means 27 e compares the address outputfrom the rendering control means 28 with the output from the selector 27d. Upon receipt of the output from the comparison means 27 e, therendering control means 28 outputs data transfer parameters to the datatransfer area setting means 21 b in the rendering data transfer means21. The parameters include the access address of the graphics commandstoring section 22 and the amount of data to be transferred which havebeen determined based on the decoding result output from the graphicscommand decoding means 25. The data transfer control means 21 a performsthe data transfer operation between the display data generation section20 and the work memory 104 via the memory interface 12 and the data bus13 according to the parameters received by the data transfer areasetting means 21 b.

[0060]FIG. 6 is a diagram illustrating a graphics command supplysequence. In FIG. 6, reference numerals 22 a and 22 b denote addressmaps of the first and second data storing means 22 a and 22 b,respectively. A first check address CHA1 is an address value whichserves as a trigger for supplying new graphics commands to the firstdata storing means 22 a, and is set in the first check address storingregister 27 a. A second check address CHA2 is an address value whichserves as a trigger for supplying new graphics commands to the seconddata storing means 22 b, and is set in the second check address storingregister 27 b. The setting of the first and second check addresses CHA1and CHA2 is done in advance by the rendering control means 28. It isassumed herein that each of the first and second check addresses CHA1and CHA2 is set to be a value in the vicinity of the maximum addressvalue for the address space. A parameter indicating which one of thefirst and second check address storing registers 27 a and 27 b is to bechecked is set in the area setting register 27 c.

[0061] In a first step S11, if neither of the first and second datastoring means 22 a and 22 b is filled with graphics commands, data isfilled in both of the first and second data storing means 22 a and 22 b.Graphics commands are filled in the first and second data storing means22 a and 22 b according to a data filling sequence FS1, e.g., in anascending order of address.

[0062] In a second step S12, the rendering control means 28 performs agraphic operation by reading out graphics commands filled in the firstdata storing means 22 a according to a data use sequence US1, e.g., inan ascending order of address. When the same address as the first checkaddress CHA1 set in the first check address storing register 27 a isaccessed, the comparison means 27 e in the address management means 27outputs an interrupt signal INT. Since the first check address CHA1 isset to a relatively large value, the output of the interrupt signal INTmeans that the graphics commands of the first data storing means 22 awill soon be exhausted, allowing for the filling of new graphicscommands in the first data storing means 22 a. At this point, the valueof the area setting register 27 c is changed.

[0063] In a third step S13, the rendering control means 28, which hasreceived the interrupt signal INT, fills new graphics commands in thefirst data storing means 22 a according to a data filling sequence FS2,e.g., in an ascending order of address. In the meantime, the graphicscommands of the second data storing means 22 b are read out and executedaccording to a data use sequence US2, e.g., in an ascending order ofaddress. When the same address as the second check address CHA2 set inthe second check address storing register 27 b is accessed, thecomparison means 27 e in the address management means 27 outputs aninterrupt signal INT.

[0064] In a fourth step S14, when the graphics commands of the firstdata storing means 22 a are being used according to a data use sequenceUS3, the rendering control means 28 fills new graphics commands in thesecond data storing means 22 b according to a data filling sequence FS3,e.g., in an ascending order of address.

[0065] The sequence of alternately repeating the third step S13 and thefourth step S14 after performing the first step S11 and the second stepS12 is performed until all graphics commands are completed or until whena special instruction, such as a rendering termination instruction, isissued.

[0066] In the sequence as illustrated in FIG. 6, when the first orsecond check address CHA1 or CHA2 is accessed, the address managementmeans 27 outputs the interrupt signal INT to the graphics prioritydetermination means 42. The graphics priority determination means 42compares the priority of the graphics command supply operation with thepriority of the data transfer operation requesting the use of the databus 13 next. If the priority of the graphics command supply operation ishigher, the graphics priority determination means 42 instructs the busmonitoring and controlling means 41 to preferentially perform thegraphics command supply operation.

[0067]FIG. 7 is a diagram illustrating a principle of operation of thepresent embodiment focusing on the operation of the first and seconddata storing means 22 a and 22 b when the graphics command decodingmeans 25 decodes a graphics command corresponding to a jump command or asubroutine command which changes the sequence of commands to beexecuted. In FIG. 7, a graphics command GI1 corresponds to a jumpcommand or a subroutine command.

[0068] The graphics command decoding means 25 sequentially takes in thegraphics commands from the first and second data storing means 22 a and22 b and decodes the graphics commands. When the graphics command GI1which changes the sequence of commands to be executed is decoded duringthe decoding operation, the graphics command decoding means 25 instructsthe rendering control means 28 to update the graphics commands stored inthe first and second data storing means 22 a and 22 b irrespective ofthe presence/absence of the output of the interrupt signal INT from theaddress management means 27. The operation of taking in the graphicscommands is performed as described above.

[0069] During such a graphics command supply sequence, there is alwaysno direct intervention of the CPU 102 or the memory 103, and therendering control means 28 independently supplies graphics commandsaccording to the status of consumption of graphics commands.

[0070] Note that data may be transferred to the graphics command storingsection 22 via the rendering data transfer means 21 or directly from thedata bus 13. Two check address storing registers are provided in theexample described above. Alternatively, for example, only one storingregister may be updated.

[0071] As described above, the graphic processor of the presentembodiment provides the management of the priorities of data transferoperations along the data bus. Therefore, even in a case of a data buswhich is connected to a system such as a unified memory and handles aplurality of types of data in a unified manner, it is possible toeffectively use the data bus without wasting a vacant status thereof.Thus, it is possible to efficiently supply graphics commands, therebyimproving the overall efficiency of the graphic processing system.

[0072] SECOND EMBODIMENT

[0073]FIG. 8 is a diagram illustrating a configuration of a graphicprocessor according to the second embodiment of the present invention.In FIG. 8, each component that is also shown in FIG. 1 is denoted by thesame reference numeral. The basic operation flow is as that of the firstembodiment. A difference from the first embodiment is that apre-decoding section 60 and a processing amount estimating section 61are added.

[0074] In a graphic processor 100A illustrated in FIG. 8, thepre-decoding section 60 pre-decodes a graphics command flowing along thedata bus 13 during a data transfer operation of transferring anexternally-input graphics command to the work memory 104. The processingamount estimating section 61 estimates the data processing amount at thedisplay data generation section 20 based on the result of thepre-decoding by the pre-decoding section 60. Specifically, for example,the data processing amount is estimated by obtaining, from thepre-decoding result, statistical data regarding the distribution oftypes of graphics commands such as a line graphics command, a polygongraphics command, etc.

[0075] In order to obtain the statistical data, weightings parametersfor determining the priorities of the line graphics command and thepolygon graphics command are set beforehand. In detail, a higherpriority is set to a polygon having more vertexes for the polygongraphics command, and each priority of a series of straight lines isdetermined according to the number of vertexes for the line graphicscommand, as illustrated in FIG. 11A.

[0076] The bus control section 40 updates the contents of the prioritysetting register 42 a of the graphics priority determination means 42and changes the setting of the priorities of data transfer operationsalong the data bus 13 according to the data processing amount estimatedby the processing amount estimating section 61. For example, when theestimated data processing amount per a predetermined period of timeexceeds a predetermined amount, the priority of the graphics commandsupply operation is increased. Specifically, the priority of the datatransfer operation of supplying a graphics command from the work memory104 to the display data generation section 20 is set to be higher thanthe priority of the data transfer operation of transferring anexternally-input graphics command to the work memory 104. In such acase, it is preferred that parameters such as the predetermined time andthe predetermined amount used for the determination can be setexternally.

[0077] As described above, according to the present embodiment, thesetting of the priorities of data transfer operations is changedaccording to an estimate processing amount for a graphics command,whereby it is possible to supply graphics commands without intermission.

[0078] THIRD EMBODIMENT

[0079]FIG. 9 is a diagram illustrating a configuration of a graphicprocessor according to the third embodiment of the present invention. InFIG. 9, each component that is also shown in FIG. 1 is denoted by thesame reference numeral. The basic operation flow is as that of the firstembodiment. A difference from the first embodiment is that a memoryinterface 12A has a memory monitor 71 for monitoring the amount of dataof the graphics commands stored in the work memory 104. Moreover, a CPU102A has an external bus monitor 72 for monitoring the amount of databeing transferred along the external bus 101.

[0080] The amount of data being transferred can be monitored byconfirming whether the data transfer is completed at every given time bytimer interruption, or by calculating the amount of data to betransferred from the data transfer length parameter indicating theamount of data of DMA to be transferred.

[0081] In a graphic processor 100B illustrated in FIG. 9, the memorymonitor 71 in the memory interface 12A monitors the amount of data ofunprocessed graphics commands stored in the work memory 104. The buscontrol section 40 updates the contents of the priority setting register42 a of the graphics priority determination means 42 and changes thesetting of the priorities of data transfer operations along the data bus13 according to the data amount monitored by the memory monitor 71. Forexample, when the monitored data amount is smaller than a predeterminedamount, the priority of the host data supply operation is increased.Specifically, the priority of the data transfer operation oftransferring an externally-input graphics command to the work memory 104is set to be higher than the priority of the data transfer operation ofsupplying a graphics command from the work memory 104 to the displaydata generation section 20. In such a case, it is preferred thatparameters such as the predetermined amount used for the determinationcan be set externally.

[0082] Moreover, the external bus monitor 72 in the CPU 102A monitorsthe amount of data being transferred along the external bus 101. The buscontrol section 40 updates the contents of the priority setting register42 a of the graphics priority determination means 42 and changes thesetting of the priorities of data transfer operations along the data bus13 according to the amount of data being transferred which is monitoredby the external bus monitor 72.

[0083] Note that the memory monitor 71 may alternatively be provided ina place other than in the memory interface 12A. The external bus monitor72 may alternatively be provided in a place other than in the CPU 102A.

[0084] Note that in each of the above-described embodiments, thefunction of determining the right to use the data bus 13 may be assignedto, for example, the CPU interface 11 or the memory interface 12,instead of assigning it to the bus monitoring and controlling means 41.

[0085] Moreover, in each of the above-described embodiments, the CPUsupplying graphics commands and various data is provided external to thegraphic processor. Alternatively, the CPU may be provided in the graphicprocessor. Also, the work memory may alternatively be provided in thegraphic processor.

What is claimed is:
 1. A graphic processor, comprising: a firstinterface for receiving an externally-input graphics command; a secondinterface for performing a data transfer operation between the graphicprocessor and a work memory; a data bus for transferring data betweenthe first interface and the second interface; a display data generationsection for receiving a graphics command from the data bus, generatingdisplay data by decoding the graphics command, and outputting thegenerated display data to the data bus; an image display section forreceiving the display data from the data bus and displaying an image ona display device; and a bus control section for monitoring a status ofuse of the data bus and controlling a right to use the data bus, whereinthe bus control section sets a priority for each data transfer operationalong the data bus and controls the right to use the data bus accordingto the set priorities.
 2. The graphic processor of claim 1 , wherein thebus control section sets a priority for each of at least the followingdata transfer operations: a data transfer operation of transferring anexternally-input graphics command to the work memory; a data transferoperation of supplying a graphics command from the work memory to thedisplay data generation section; and a data transfer operation ofsupplying display data from the work memory to the image displaysection.
 3. The graphic processor of claim 1 , wherein the bus controlsection is configured so that a setting of the priorities of datatransfer operations can be changed dynamically.
 4. The graphic processorof claim 3 , further comprising: a pre-decoding section for pre-decodinga graphics command transferred during a data transfer operation oftransferring an externally-input graphics command to the work memory;and a processing amount estimating section for estimating a dataprocessing amount at the display data generation section based on aresult of the pre-decoding by the pre-decoding section, wherein the buscontrol section changes the priorities of the data transfer operationsaccording to the data processing amount estimated by the processingamount estimating section.
 5. The graphic processor of claim 4 , whereinwhen the estimated data processing amount per a predetermined period oftime exceeds a predetermined amount, the bus control section sets thepriority of a data transfer operation of supplying a graphics commandfrom the work memory to the display data generation section to be higherthan the priority of a data transfer operation of transferring anexternally-input graphics command to the work memory.
 6. The graphicprocessor of claim 3 , further comprising a memory monitor formonitoring an amount of data of graphics commands stored in the workmemory, wherein the bus control section changes the priorities of thedata transfer operations according to the data amount monitored by thememory monitor.
 7. The graphic processor of claim 6 , wherein when themonitored data amount is smaller than a predetermined amount, the buscontrol section sets the priority of a data transfer operation oftransferring an externally-input graphics command to the work memory tobe higher than the priority of a data transfer operation of supplying agraphics command from the work memory to the display data generationsection.
 8. The graphic processor of claim 3 , wherein: the firstinterface is connected to an external bus which is provided external tothe graphic processor; an external bus monitor for monitoring an amountof data being transferred along the external bus is connected to theexternal bus; and the bus control section changes the priorities of thedata transfer operations along the data bus according to the amount ofdata being transferred which is monitored by the external bus monitor.9. The graphic processor of claim 1 , wherein: the display datageneration section includes a graphics command storing section fortemporarily storing a graphics command which is input through the databus, and a decoding section for decoding a graphics command which isoutput from the graphics command storing section; the graphics commandstoring section includes first data storing means and second datastoring means, writes graphics commands into selected one of the firstand second data storing means in a predetermined address order, andreads out graphics commands from selected one of the first and seconddata storing means in a predetermined address order; and when a readingaddress in one of the first and second data storing means from whichgraphics commands are being read out matches a predetermined checkaddress, the graphics command storing section starts writing newgraphics commands into the one of the first and second data storingmeans.
 10. A graphic processing system, comprising: the graphicprocessor of claim 1 ; an external bus connected to the first interfaceof the graphic processor; a CPU and a memory which are connected to theexternal bus; a work memory connected to the second interface of thegraphic processor; and a display device connected to the image displaysection of the graphic processor.
 11. A graphic processor, comprising: afirst interface for receiving an externally-input graphics command; asecond interface for performing a data transfer operation between thegraphic processor and a work memory; a data bus for connecting the firstinterface with the second interface; a display data generation sectionfor receiving a graphics command from the data bus, generating displaydata by decoding the graphics command, and outputting the generateddisplay data to the data bus; and an image display section for receivingthe display data from the data bus and displaying an image on a displaydevice, wherein: the display data generation section includes a graphicscommand storing section for temporarily storing a graphics command whichis input through the data bus, and a decoding section for decoding agraphics command which is output from the graphics command storingsection; the graphics command storing section includes first datastoring means and second data storing means, writes graphics commandsinto selected one of the first and second data storing means in apredetermined address order, and reads out graphics commands fromselected one of the first and second data storing means in apredetermined address order; and when a reading address in one of thefirst and second data storing means from which graphics commands arebeing read out matches a predetermined check address, the graphicscommand storing section starts writing new graphics commands into theone of the first and second data storing means.